1. Field of the Invention
This invention relates to a nonvolatile semiconductor memory, a method for data readout thereof, and a memory card, and in particular relates to an electrically erasable type nonvolatile semiconductor memory, a method for reading out data and a memory card in which an electrically erasable type nonvolatile semiconductor memory is mounted.
2. Description of the Related Art
In recent years, among semiconductor memories, a nonvolatile semiconductor memory in which the programmed data are in a nonvolatile way held is diffused. In the nonvolatile semiconductor memory, electrically erasable type nonvolatile semiconductor memory having a NAND type memory cell array (hereinafter will be simply called as a NAND type nonvolatile semiconductor memory) is suitable for enlarging storage capacity.
In a memory cell array of the NAND type nonvolatile semiconductor memory, a plurality of memory cell units are disposed in a matrix shape. One memory cell of the memory cell units is constituted by an electric filed effect transistor. The electric filed effect transistor having an electric charge accumulation layer, a control electrode, a source region and a drain region. This electric charge accumulation layer is electrically floating. The memory cell unit provides with a plurality of memory cells that is electrically connected in series, a drain side selection transistor that is connected to a drain region of one end of the plurality of memory cells, and a source side selection transistor that is connected to a source region of the other side of the plurality of the memory cells.
In the memory cell units, the source region and the drain region of the memory cells that are mutually adjacent are shared. In the respective control electrodes of the plurality of memory cells, word lines, in which the memory cell array is extended, are electrically connected. Further, in a drain region of one end of memory cell of the memory cell units, a bit line is connected via a drain side selection transistor. In a gate electrode of the drain side selection transistor, a drain side gate line is connected. In a source region of the other side of memory cell of the memory cell units, a source line is connected via a source side selection transistor. In a gate electrode of the source side selection transistor, a source side selected gate line is connected. In the NAND type nonvolatile semiconductor memory, a decoder, a data programming circuit, a data readout circuit and so forth are disposed.
In a data programming operation of the NAND type nonvolatile semiconductor memory, data may be programmed in a selected memory cell by applying an appropriate program voltage, a control voltage and so forth, to each of: a being selected word line, a selected bit line, a selected source line, a selected drain side selected gate line, and a selected source side selected gate line. On the other hand, data is not programmed in non selected memory cells by applying a non-program voltage, a control voltage and so forth, to a being non-selected word lines and so forth.
In addition to above, related art in respect to a data programming operation are disclosed in JP H08-55488 A, and JP 2000-173300 A, respectively.
Further, the data readout operation of the NAND type nonvolatile semiconductor memory are performed in the following procedure. Firstly, the voltage of the selected drain side selected gate line is boosted, for instance, to a degree of 4V so that the selected drain side selected transistor is made be in an on-state; subsequently, a voltage of about 1V is applied to the selected bit line; and a readout voltage is applied to the selected word line that is connected to the selected memory cell. On the other hand, the voltage of the non-selected word line that is connected to the non-selected memory cells other than the selected memory cell is boosted, for instance, to a degree of 5V so that the non-selected memory cells made be in an on-state. Afterwards, the voltage of the source side selected gate line is boosted, for instance, to a degree of 4V so that the source side selected gate transistor is made be in an on-state. Then, detecting the voltage change of the selected bit line generated by this result, whether “0” data or “1” data are stored in the selected memory cell.
In addition the related art in respect to a data readout operation is disclosed in JP 2005-108404 A.